Today's data processing systems often require the transfer of large volumes of information in as short a time as possible. When the data processing system is incorporated onto one or a few integrated circuits, the requirement of minimal semiconductor area is usually added.
Most microprocessors use one or more busses to transfer information, such as data, address, and control, from various portions of the integrated circuit. A problem arises when two or more registers are to be read or written concurrently and there is only one available bus to access both registers. A variety of possible solutions to this problem have been used in the past. For example, one solution is merely to add an additional bus or extend an existing bus so that both registers can be written concurrently using two different busses. The drawback to this solution is that it may require a prohibitive amount of semiconductor area, especially as the size of microprocessor chips increases and busses must be routed long distances.
Another possible solution is to use the existing bus structure to first write one register and then the other register. Although this solution does not require more semiconductor area, it does require more time. In addition, the fact that the two registers are no longer accessed concurrently creates a coherency problem between the data in the first register and the data in the second register. In order to maintain coherency in the data being transferred to or from the two registers, the existing bus to the two registers may have to be locked in order to prevent intervening accesses to the two registers. Alternatively, a status bit could be used in order to indicate whether or not coherency had been maintained.